The present disclosure relates to technology for non-volatile storage.
Semiconductor memory is used in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
Some non-volatile memory store information in a charge storage region that is insulated from a channel region in a semiconductor substrate. As one example, a floating gate is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is located between the source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
Some non-volatile memory utilizes a charge trapping layer to store information. One such example is an oxide-nitride-oxide (ONO) region, in which the nitride (e.g., SiN) serves as a charge trapping layer to store information. When such a memory cell is programmed, electrons are stored in the charge trapping layer.
In one architecture, the memory cells are part of a NAND string. A NAND string includes series of memory cells between a drain side select gate and a source side select gate. The drain side select gate switchably connects one end of the NAND string to a bit line. The source side select gate switchably connects the other end of the NAND string to a common source line, which is connected to many NAND strings.
Non-volatile memory could have a 2D architecture or a 3D architecture. Recently, ultra high density storage devices have been proposed using a 3D stacked memory structure having strings of memory cells. One such storage device is sometimes referred to as a Bit Cost Scalable (BiCS) architecture. For example, a 3D NAND stacked memory device can be formed from an array of alternating conductor and insulator layers. A memory hole is drilled in the layers to define many memory layers simultaneously. A NAND string is then formed by filling the memory hole with appropriate materials. A straight NAND string extends in one memory hole, while a pipe- or U-shaped NAND string (P-BiCS) includes a pair of vertical columns of memory cells which extend in two memory holes and which are joined by a pipe connection. Control gates of the memory cells are provided by the conductor layers. Other techniques can be used to form 3D NAND.